Conventional communication means in general communication equipment for wire communication, radio communication and the like in many cases adopts a construction shown in FIG. 1. As shown in FIG. 1, in communication means 1, input data introduced as conventional communication data through an input end is passed through input interface means 2 and is supplied to buffering means 4 while controlling by communication control means 3 to perform buffering. Further, the input data is subjected to protocol conversion processing in protocol conversion means 5, is then withdrawn from the buffering means 4, is passed through output interface means 6, and is output through an output end.
Here input of data into the communication means (apparatus) 1, that is, the arrival of data, sometimes occurs in such a state that the preparation of the communication means 1 for receiving the input is incomplete. Therefore, the data should be temporarily maintained (buffered) until the preparation for receiving data is complete. Accordingly, the buffering means 4 temporarily maintains (buffers) input data, until the communication means 1 is ready for the receipt of the data, and performs speed buffering. Regarding the buffering means 4, there are many types which, according to the construction of the system, range from one, which requires large buffering, to one which simply permits passage of signals without protocol conversion or the like.
FIG. 2 is a diagram showing the construction of an example of a conventional buffering apparatus. In this drawing, a buffering apparatus 10 is an apparatus for realizing the buffering means 4 shown in FIG. 1 and comprises buffer means 11 comprising n first-in-first-out buffers (FIFOS) or the like and buffer control means 12. The buffer control means 12 comprises buffer write control means 13 for controlling the writing operation of the buffer means 11, buffer read control means 14 for controlling the read operation of the buffer means 11, and buffer access control means 15 for controlling the buffer write control means 13 and the buffer read control means 14.
Further, input control means 16, output control means 17, address administration means 1l, and address control means 19 are provided outside the buffering apparatus 10. As shown in FIG. 3, the input control means 16 comprises input address detection means 161, input address notification means 162, input signal control means 163, and buffer write request control means 164. As shown in FIG. 4, the output control means 17 comprises buffer read request control means 171, output address control means 172, output signal control means 173, and bus width selection means 174.
As shown in FIG. 5, the address administration means 18 comprises address input means 181 and address notification means 182. The address control means 19 comprises address designation interface means 191. On the assumption that DMA or the like is used, the address control means 19 exists in such a case that the address information is separately administered by a processor such as an external central processing unit (CPU). Upon the receipt of addressing from an external part, the address designation interface means 191 directly or indirectly accesses the address administration means 18. As shown in FIG. 6, the buffer means 11 uses a write pointer (BUFWP) and a read pointer (BUFRP) for the buffer (BUF) to simply render the operation for storing data into the buffer continuous and thus to store a group of a series of data.
Next, the operation of the conventional buffering apparatus 10 will be briefly explained. As soon as a certain group of a series of data such as a frame and a packet externally arrives at the input control means 16, the input control means 16 transfers the group of input data to the buffer control means 12. The buffer control means 12 is mainly responsible for the control of writing into the buffer means 11 and reading of data from the buffer means 11 and sequentially writes and stores the group of input data into the buffer means 11.
When the preparation on the output side has been completed, processing for outputting is started by the buffer control means 12. The series of data group is read from the buffer means 11, is passed through the output control means 17. and is output. In outputting the series of data, the output control means 17 selects output bus width, and the data are divided into or integrated into necessary data width followed by outputting.
Here when the bus on the side of input into the buffering apparatus 10 is an address data bus which contains an address by time division, the input control means 16 separates address information from the bus and notifies the address administration means is of the address. The address administration means is maintains the address and sends the address information to the buffer access control means 15 in synchronization with the time of output of the series of data group. In the prior art technique, since the construction of juxtaposed buffers is simple, the address administration means 18 has the function of maintaining the input address as it is until the address is output.
Further, the conventional construction is generally such that, upon the receipt of a request from the external part for output from the buffer, data is fetched from the buffer according to the request. The requirement for the start of reading of the data is that necessary data length has been stored in the buffer. Here whether or not the necessary data length has been stored in the buffer is examined for the juxtaposed buffers.
Another example of the conventional buffering apparatus is disclosed in Japanese Patent No. 2642652(Japanese Patent Laid-Open No. 198143/1989. This conventional buffering apparatus comprises: a double buffer comprising first and second buffers which absorb a fluctuation in input packet data, which arrive at irregular timing, and send output data at fixed timing, the first and second buffers being alternately switchable on the input side and the output side; a buffer control unit for monitoring data capacity within the double buffer and controlling the switching of the double buffer using one packet data output period as the shortest switching unit period; FIFO provided on the input side of the double buffer, for buffering the input packet data; and an FIFO control unit for controlling the transfer of data from the FIFO to the double buffer according to the switching of the buffer by the buffer control unit. According to this construction, a fluctuation in packet data, which arrives at irregular timing, is absorbed to prevent one packet data from being divided into a plurality of parts which are stored in a plurality of buffers.
The conventional buffering apparatuses have the following problems. At the outset, in many cases, the buffering apparatus is mounted completely separately from the bus width selection means, and, thus, due to the form of mounting, the optimization of processing is difficult. Specifically, within the communication means 1 shown in FIG. 1, under control by the communication control means 3 and the protocol conversion means 4, a decision is made on branching for processing, and the bus width selection means for selecting the bus width necessary for the processing is provided for speed buffering for absorbing the processing time difference and performs bus width conversion for enhancing the capacity of processing at a time per unit time.
This bus width selection means can be realized, for example, in a construction disclosed in Japanese Patent Laid-Open No. 2659401/1993, that is, a construction wherein, in a module comprising an asynchronous buffer memory provided integrally with a group of data width conversion buffers some of multiple input 8 bits are combined, and bus width conversion is performed for 32-bit output (or output of less than 32 bits).
Here, for example, when real-time processing is necessary, assuming that one-byte input data is present for each clock, in the processing within the device (communication means 1), if 2 clocks are used for one byte, processing cannot catch up with input data. In this case, input data overflow, and the processing fails. When the processing method and bus width are converted in such a manner that, within the device (communication means 1), for example, two bytes can be processed per clock, the same speed as the input data can be apparently realized. The bus width selection means is means for this bus width conversion. Since, however, in the prior art technique, the bus width selection means is provided completely separately from the buffering apparatus, it is difficult to optimally covert buffer bus width and output bus width.
The second problem of the conventional apparatus is that, since the buffering apparatus 10 is provided completely separately from the address administration means 18, this construction is inefficient when there are a plurality of bus widths in such a state that a plurality of data groups are simultaneously buffered. As found in conventional means, in many cases, buffer function and address administration function are divided into separate construction blocks, and pure buffer is provided independently of pure data transfer such as DMA. Since, however, signal line is managed for each bus width, signal lines, for which common control is possible, are managed separately from each other or one another. This is inefficient.
The third problem of the conventional apparatus is as follows. The buffer in the buffer means 11 and the double buffer in the buffering apparatus disclosed in Japanese Patent No. 2642652 are fixedly present with respect to the maximum storage data length, and a problem exists in a physical structural buffer construction wherein a series of data groups are selected and retrieved from a plurality of maximum fixed length buffers. For example, when several maximum data length fixed buffers, which are extensively used in the conventional buffering apparatus, are provided, even though the length of a certain data group does not reach the maximum data length, the idle portion cannot be allocated to a different data group.